The present invention relates to a data storing method of a dynamic RAM (Random Access Memory) and a semiconductor memory device and, more particularly, to a technique effective for use in a data storing technique in a memory circuit having dynamic memory cells.
It was found by the search made after the present invention was achieved that Japanese Unexamined Patent Publication Nos. Hei 11(1999)-213659 (corresponding to U.S. Pat. No. 6,199,139, hereinbelow, called prior art 1) and Hei 7(1995)-262794 (hereinbelow, called prior art 2) seem to be related to the present invention to be described hereinlater. According to prior art 1, to optimize the refresh cycle interval of a DRAM in a sleep mode, the frequency of the refresh cycle is controlled by software under the control of a CPU by using the number of error rows detected by an error correction decoding circuit. According to prior art 2, an ECC circuit is provided in a DRAM, an error is detected, and corrected data is written in a memory cell. In the prior arts, there is no description suggesting that lower power consumption is realized with a simple configuration like the present invention as will be described hereinlater.
Japanese Unexamined Patent Publication No. Hei 11-213659 discloses a technique of optimizing the refresh interval of a memory circuit in a sleep mode by using an error correction coding circuit, an error correction decoding circuit, a refresh interval control circuit, a refresh executing circuit, and the like.
Japanese Unexamined Patent Publication No. 2000-11688 discloses a technique of realizing lower power consumption in a self refresh mode and increased manufacturing yield by the following method. When a dynamic RAM enters a self refresh mode, internal control signals EC and EW for a sense amplifier SA and an ECC circuit ECC go high, thereby making the ECC circuit ECC selectively operative. JP-A Hei 3(1991)-23587 discloses a technique of generating and writing a parity bit and making a parity check at the time of a refresh.
Japanese Unexamined Patent Publication No. Hei 10(1998)-177800 discloses an error correcting dynamic memory having an error correcting circuit for executing error correction during a refresh of a plurality of dynamic memory cells and omitting error correction on a first sequence of one or more cells out of the plurality of dynamic memory cells.
Japanese Unexamined Patent Publication No. Hei 9(1997)-91206 discloses a DRAM in which a read cycle for detecting an error is executed in each refresh cycle and, when an error exists, corrected data is rewritten as necessary.
Japanese Unexamined Patent Publication No. Hei 4(1992)-149899 discloses a technique of adding an ECC for each word line to check data during a refresh cycle even when there is no access in order to built a very reliable memory system.
Japanese Unexamined Patent Publication No. Hei 7(1995)-262794 discloses a technique of providing an error correcting circuit in a memory chip of a memory required to be data-refreshed, from/to which data can be always read/written, collating data for an error detection and correction code with data read from the memory in a refresh cycle and, when an error is detected, writing error-detected data into the memory.